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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this produ ct without notice. copyright ? cirrus logic, inc. 2004 (all rights reserved) http://www.cirrus.com features ? 1.8 to 3.3 volt supply ? 24-bit conversion / 96 khz sample rate ? 96 db dynamic range at 3 v supply ? -85 db thd+n ? low power consumption ? digital volume control ? 96 db attenuation, 1 db step size ? digital bass and treble boost ? selectable corner frequencies ? up to 12 db boost in 1 db increments ? peak signal limiting to prevent clipping ? de-emphasis for 32 khz, 44.1 khz, and 48 khz ? headphone amplifier ? up to 25 mw rms power output into 16 ? load* ? 25 db analog attenuation and mute ? zero crossing click free level transitions ? atapi mixing functions ? 24-pin tssop package * 1 khz sine wave at 3.3v supply description the cs43l42 is a complete stereo digital-to-analog out- put system including interpol ation, 1-bit d/a conversion, analog filtering, volume cont rol, line level outputs, and a headphone amplifier, in a 24-pin tssop package. the cs43l42 is based on delta-sigma modulation, where the modulator output controls the reference volt- age input to an ultra-linear analog low-pass filter. this architecture allows infinite adjustment of the sample rate between 2 khz and 100 khz simply by changing the master clock frequency. the cs43l42 contains on-chip digital bass and treble boost, peak signal limiting, and de-emphasis. the cs43l42 operates from a +1.8 v to +3.3 v supply and consumes only 16 mw of power with a 1.8 v supply with the line amplifier powered-down. these features are ideal for portable cd, mp3 and md players and other portable playback systems that require extremely low power consumption. ordering in formation cs43l42-kz -10 to 70 c 24-pin tssop CS43L42-KZZ, lead free -10 to 70 c 24-pin tssop cdb43l42 evaluation board scl/cclk/dif1 sda/cdin/dif0 ad0/cs/dem0 mutec control port digital volume control bass/treble boost limiting analog filter analog filter hp_a hp_b aouta aoutb rst lrck sclk/dem1 sdata serial port de-emphasis digital filters ? dac ? dac headphone amplifier external mute control analog volume control mclk analog volume control line amplifier compensation g a i n va_hp va_line va vl gnd vq_hp filt+ ref_gnd vq_line cs43l42 low voltage, stereo da c with headphone amp sep ?04 ds481pp2
cs43l42 2 ds481pp2 table of contents 1. characteristics/specifications ....................................................... 5 analog characteristics................................................................... 5 analog characteristics................................................................... 6 analog characteristics................................................................... 7 power and thermal characteristics ......................................... 8 digital characteristics.................................................................... 9 absolute maximum rating s ................ ................ ................ .............. 9 recommended operating conditions .......................................... 9 switching characteristics ........................................................... 10 switching characteristics - co ntrol port - two-wire mode12 switching characteristics - control port - spi mode....... 13 2. typical connection diagram .......................................................... 14 3. register quick reference ................................................................ 15 4. register description .......................................................................... 16 4.1 power and muting control (address 01h) .......................................... 16 4.1.1 auto-mute (amute) ........................................................................ 16 4.1.2 soft ramp and zero cross control (szc) ................................ 16 4.1.3 popguard? transient control (por)............................................... 17 4.1.4 power down headphone amplifier (pdnhp)................................... 17 4.1.5 power down line am plifier (pdnln) ............................................... 17 4.1.6 power down (pdn) .......................................................................... 17 4.2 channel a analog headphone attenuation control (address 02h) (hvola)18 4.3 channel b analog headphone attenuation control (address 03h) (hvolb)18 4.4 channel a digital volu me control (address 04h) (dvola) ............... 18 4.5 channel b digital volu me control (address 05h) (dvolb) ............... 18 4.6 tone control (address 06h)................................................................ 19 4.6.1 bass boost level (bb)...................................................................... 19 4.6.2 treble boost level (tb) ..................................................................... 19 4.7 mode control (address 07h) ............................................................... 20 4.7.1 bass boost corner frequency (bbcf) ............................................... 20 4.7.2 treble boost corner frequency (tbcf)........................................... 20 4.7.3 channel a volume = channel b volume (a=b) ............................... 20 4.7.4 de-emphasis control (dem) ............................................................ 21 4.7.5 digital volume co ntrol bypass (vcbyp).......................................... 21 4.8 limiter attack rate (address 08h) (arate)....................................... 21 4.9 limiter release rate (address 09h) (rrate) ............................... 22 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit t he cirrus logic web site at: http://www.cirrus.com/corporate/contacts/ i 2 c is a registered trademark of philips semiconductors. preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best effort s to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provi ded ?as is? without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. for the use of this information, nor for inf ringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, tradem arks, or trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electron ic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc. items from any cirrus logic website or disk may be printed for use by the user. however, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form o r by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc.furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. the names of products of cirrus logic, inc. or ot her vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. a list of cirrus logic, inc. trade- marks and service marks can be found at http://www.cirrus.com.
cs43l42 ds481pp2 3 4.10 volume and mixing control (address 0ah)....................................... 22 4.10.1 tone control mode (tc)......... ...................................................... 22 4.10.2 tone control enable (tc_en) . ...................................................... 22 4.10.3 peak signal limiter enable (l im_en) ............................................ 23 4.10.4 atapi channel mixing and muti ng (atapi) ..................................... 23 4.11 mode control 2 (address 0bh) ......................................................... 24 4.11.1 master clock divide enable (mclkdiv) ....................................... 24 4.11.2 line amplifier ga in compensation (line) ........................................ 24 4.11.3 digital interface format (dif) ........................................................... 24 5. pin description ....................................................................................... 26 6. applications ........................................................................................... 29 6.1 grounding and power supply dec oupling ........................................ 29 6.2 clock modes ...................................................................................... 29 6.3 de-emphasis ..................................................................................... 29 6.4 recommended power-up sequence ................................................ 29 6.5 popguard? transient control ........................................................... 29 7. control port interface .................................................................... 30 7.1 spi mode ........................................................................................... 30 7.2 two-wire mode ................................................................................. 30 7.3 memory address pointer (map) ............................................... 31 7.3.1 incr (auto map increment enable)................................................. 31 7.3.2 map0-3 (memory ad dress pointer) ................................................. 31 8. parameter definitions ........................................................................ 39 9. references .............................................................................................. 39 10. package dimensions ......................................................................... 40 list of figures figure 1. external serial mode input timi ng ............................................................ 11 figure 2. internal serial mode input timi ng ............................................................. 11 figure 3. internal serial clock generation ............................................................... 11 figure 4. control port timing - two-wire mode ....................................................... 12 figure 5. control port timing - spi mode ................................................................ 13 figure 6. typical connection diagram ..... ................................................................ 14 figure 7. control port timing, spi mode .................................................................. 31 figure 8. control port timing, two-wire mode ........................................................ 31 figure 9. base-rate stopband rejection . ................................................................ 32 figure 10. base-rate transi tion band ..................................................................... 32 figure 11. base-rate transition band (detai l) ......................................................... 32 figure 12. base-rate passba nd ripple ................................................................... 32 figure 13. high-rate stopband rejection ................................................................ 32 figure 14. high-rate transit ion band ...................................................................... 32 figure 15. high-rate transitio n band (detail) ......................................................... 33 figure 16. high-rate passband ripple .... ................................................................ 33 figure 17. line output test load ............................................................................. 33 figure 18. headphone output test load ................................................................. 33 figure 19. cs43l42 control port mode - serial audio format 0 ............................. 34 figure 20. cs43l42 control port mode - serial audio format 1 ............................. 34 figure 21. cs43l42 control port mode - serial audio format 2 ............................. 34 figure 22. cs43l42 control port mode - serial audio format 3 ............................. 35 figure 23. cs43l42 control port mode - serial audio format 4 ............................. 35 figure 24. cs43l42 control port mode - serial audio format 5 ............................. 35 figure 25. cs43l42 control port mode - serial audio format 6 ............................. 36 figure 26. cs43l42 stand alone mode - serial audio format 0 ............................. 36
cs43l42 4 ds481pp2 figure 27. cs43l42 stand alone mode - serial audio format 1 ............................. 36 figure 28. cs43l42 stand alone mode - serial audio format 2 ............................. 37 figure 29. cs43l42 stand alone mode - serial audio format 3 ............................. 37 figure 30. de-emphasis curve ................. ................................................................ 38 figure 31. atapi block diagram .............. ................................................................ 38 list of tables table 1. example analog volume settings ............................................................... 18 table 2. example digital volume settings ................................................................ 19 table 3. example bass boost settings ..................................................................... 19 table 4. example treble boost settings ................................................................... 19 table 5. example limiter attack rate settin gs ......................................................... 21 table 6. example limiter release rate se ttings ..................................................... 22 table 7. atapi decode ............................................................................................ 23 table 8. digital interface fo rmat ............................................................................... 25 table 9. stand alone de-emphasis control ............................................................. 27 table 10. hrm common clock frequencies ........................................................... 27 table 11. brm common clock frequencies ............................................................ 27 table 12. digital interface format - dif1 and dif0 (stand-alone mode) ................ 28 table 13.
cs43l42 ds481pp2 5 1. characteristics/specifications analog characteristics (t a = 25 c; logic "1" = vl = 1.8 v; logic "0" = gnd = 0 v; full-scale output sine wave, 997 hz; mclk = 12.288 mh z; measurement bandwidth 10 hz to 20 khz, unless oth- erwise specified; fs for base-rate mode = 48 khz, sclk = 3.072 mh z. fs for high-rate mode = 96 khz, sclk = 6.144 mhz. test load r l =10k ? , c l = 10 pf (see figure 17) for line out, r l =16 ? , c l = 10 pf (see fig- ure 18) for headphone out). notes: 1. one-half lsb of triangular pdf dither is added to data. parameter base-rate mode high-rate mode symbol min typ max min typ max unit line output dynamic performance for va = va_line = 1.8 v dynamic range (note 1) 18 to 24-bit unweighted a-weighted 16-bit unweighted a-weighted tbd tbd - - 91 94 89 92 - - - - tbd tbd - - 89 92 87 90 - - - - db db db db total harmonic distortion + noise (note 1) 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db thd+n - - - - - - -80 -71 -31 -78 -69 -29 tbd - - - - - - - - - - - -80 -69 -29 -78 -67 -27 tbd - - - - - db db db db db db interchannel isolation (1 khz) - 100 - - 100 - db headphone output dynamic performance for va = va_hp = 1.8 v dynamic range (note 1) 18 to 24-bit unweighted a-weighted 16-bit unweighted a-weighted tbd tbd - - 88 91 86 89 - - - - tbd tbd - - 88 91 86 89 - - - - db db db db total harmonic distortion + noise (note 1) 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db thd+n - - - - - - -82 -68 -28 -80 -66 -26 tbd - - - - - - - - - - - -85 -68 -28 -83 -66 -26 tbd - - - - - db db db db db db interchannel isolation (1 khz) - 66 - - 66 - db
cs43l42 6 ds481pp2 analog characteristics (continued) parameter base-rate mode high-rate mode symbol min typ max min typ max unit line output dynamic performance for va = va_line = 3.0 v dynamic range. (note 1) 18 to 24-bit. unweighted a-weighted 16-bit. unweighted a-weighted tbd tbd - - 93 96 91 94 - - - - tbd tbd - - 93 96 91 94 - - - - db db db db total harmonic distortion + noise. (note 1) 18 to 24-bit. 0 db -20 db -60 db 16-bit. 0 db -20 db -60 db thd+n - - - - - - -85 -73 -33 -83 -71 -31 tbd - - - - - - - - - - - -85 -73 -33 -83 -71 -31 tbd - - - - - db db db db db db interchannel isolation. (1 khz) - 100 - - 100 - db headphone output dynamic performance for va = va_hp = 3.0 v dynamic range. (note 1) 18 to 24-bit. unweighted a-weighted 16-bit. unweighted a-weighted tbd tbd - - 90 93 88 91 - - - - tbd tbd - - 90 93 88 91 - - - - db db db db total harmonic distortion + noise. (note 1) 18 to 24-bit. 0 db -20 db -60 db 16-bit. 0 db -20 db -60 db thd+n - - - - - - -76 -70 -30 -74 -68 -28 tbd - - - - - - - - - - - -73 -70 -30 -71 -68 -28 tbd - - - - - db db db db db db interchannel isolation. (1 khz) - 66 - - 66 - db
cs43l42 ds481pp2 7 analog characteristics (continued) notes: 2. see line amplifier gain compensation (line) for details. 3. filter response is not tested but is guaranteed by design. 4. response is clock dependent and will scale with fs. no te that the response plots (figures 9-16) have been normalized to fs and can be de-normalized by multiplying the x- axis scale by fs. 5. referenced to a 1 khz , full-scale sine wave. 6. for base-rate mode, the measurement bandwidth is 0.5465 fs to 3 fs. for high-rate mode, the measurement bandwidth is 0.577 fs to 1.4 fs. 7. de-emphasis is not available in high-rate mode. parameters symbol min typ max units analog output full scale line output voltage (note 2) v fs_line tbd g x va tbd vpp line output quiescent voltage v q_line - 0.5 x va_line - vdc full scale headphone output voltage v fs_hp tbd 0.55 x va tbd vpp headphone output quiescent voltage v q_hp - 0.5 x va_hp - vdc interchannel gain mismatch - 0.1 - db gain drift - 100 - ppm/c maximum line output ac-current va=va_line=1.8 v va=va_line=3.0 v i line - - 0.1 0.15 - - ma ma maximum headphone output va=va_hp=1.8 v ac-current va=va_hp=3.0 v i hp - - 31 52 - - ma ma parameter base-rate mode high-rate mode symbol min typ max min typ max unit combined digital and on-chip analog filter response (note 3) passband (note 4) to -0.05 db corner to -0.1 db corner to -3 db corner 0 - 0 - - - .4535 - .4998 - 0 0 - - - - .4426 .4984 fs fs fs frequency response 10 hz to 20 khz (note 5) -.02 - +.08 0 - +0.11 db stopband .5465 - - .577 - - fs stopband attenuation (note 6) 50 - - 55 - - db group delay tgd - 9/fs - - 4/fs - s passband group delay deviation 0 - 40 khz 0 - 20 khz - - - 0.36/fs - - - - 1.39/fs 0.23/fs - - s s de-emphasis error fs = 32 khz (relative to 1 khz) fs = 44.1 khz fs = 48 khz - - - - - - +.2/-.1 +.05/-.14 +0/-.22 (note 7) db db db
cs43l42 8 ds481pp2 power and thermal characteristics (gnd = 0 v; all voltages with respect to ground. all measurements taken with all zeros inpu t and open outputs, unless otherwise specified.) notes: 8. power down mode is defined as rst = lo with all clocks and data lines held static. 9. valid with the recommended capacitor values on filt+, vq_line and vq_hp as shown in figure 6. increasing the capacitance will also increase the psrr. note that care should be taken when selecting capacitor type, as any leakage current in excess of 1.0 a will cause degradation in analog performance. parameters symbol min typ max units power supplies power supply current- va=1.8 v normal operation va_hp=1.8 v va_line=1.8 v vl=1.8 v i a i a_hp i a_line i d_l - - - - 7.3 1.5 1.6 4 - - - - ma ma ma a power supply current- va=1.8 v power down mode (note 8) va_hp=1.8 v va_line=1.8 v vl=1.8 v i a i a_hp i a_line i d_l - - - - tbd tbd tbd tbd - - - - a a a a power supply current- va=3.0 v normal operation va_hp=3.0 v va_line=3.0 v vl=3.0 v i a i a_hp i a_line i d_l - - - - 10.5 1.5 1.7 9.3 - - - - ma ma ma a power supply current- va=3.0 v power down mode (note 8) va_hp=3.0 v va_line=3.0 v vl=3.0 v i a i a_hp i a_line i d_l - - - - tbd tbd tbd tbd - - - - a a a a total power dissipation- all supplies=1.8 v normal operation all supplies=3.0 v - - 19 41 tbd tbd mw mw maximum headphone power dissipation (1 khz full-scale sine wave va=1.8 v into 16 ohm load) va=3.0 v - - tbd tbd - - mw mw package thermal resistance ja -75-c/watt power supply rejection ratio (note 9) (1 khz) (60 hz) psrr - - 60 40 - - db db
cs43l42 ds481pp2 9 digital characteristics (t a = 25 c; vl = 1.7 v - 3.6 v; gnd = 0 v) absolute maximum ratings (gnd = 0v; all voltages with respect to ground.) warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (gnd = 0v; all voltages with respect to ground.) notes: 10. to prevent clipping the outputs, va_hp min is limited by the full- scale output voltage v fs_hp , where va_hp must be 200 mv greater than v fs_hp . however, if distortion is not a concern, va_hp may be as low as 0.9 v at any time. parameters symbol min typ max units high-level input voltage v ih 0.7 x vl - - v low-level input voltage v il - - 0.3 x vl v input leakage current i in --10 a input capacitance - 8 - pf maximum mutec drive capability va=1.8 v va=3.0 v - - tbd 3 - - ma ma mutec high-level output voltage - va - v mutec low-level output voltage - 0 - v parameters symbol min max units dc power supplies: positive analog headphone line digital i/o va va_hp va_line vl -0.3 -0.3 -0.3 -0.3 4.0 4.0 4.0 4.0 v v v v input current, any pin except supplies i in -10ma digital input voltage v ind -0.3 vl+0.4 v ambient operating temperature (power applied) t a -55 125 c storage temperature t stg -65 150 c parameters symbol min typ max units ambient temperature t a -10 - 70 c dc power supplies: positive analog headphone (note 10) line digital i/o va va_hp va_line vl 1.7 0.9 va 1.7 - - - - 3.6 3.6 3.6 3.6 v v v v
cs43l42 10 ds481pp2 switching characteristics (t a = -10 to 70 c; vl = 1.7 v - 3.6 v; inputs: logic 0 = gnd, logic 1 = vl, c l =20pf) notes: 11. internal sclk mode timing is not tested, but is guaranteed by design. 12. in internal sclk mode, the lrck duty cycle must be 50% +/? 1/2 mclk period. parameters symbol min typ max units input sample rate base rate mode high rate mode fs fs 2 50 - - 50 100 khz khz mclk pulse width high mclk/lrck = 1024 7 - - ns mclk pulse width low mclk/lrck = 1024 7 - - ns mclk pulse width high mclk/lrck = 768 10 - - ns mclk pulse width low mclk/lrck = 768 10 - - ns mclk pulse width high mclk/lrck = 512 15 - - ns mclk pulse width low mclk/lrck = 512 15 - - ns mclk pulse width high mclk / lrck = 384 or 192 25 - - ns mclk pulse width low mclk / lrck = 384 or 192 25 - - ns mclk pulse width high mclk / lrck = 256 or 128 35 - - ns mclk pulse width low mclk / lrck = 256 or 128 35 - - ns external sclk mode lrck duty cycle (external sclk only) 40 50 60 % sclk pulse width low t sclkl 20 - - ns sclk pulse width high t sclkh 20 - - ns sclk period base rate mode t sclkw --ns high rate mode t sclkw --ns sclk rising to lrck edge delay t slrd 20 - - ns sclk rising to lrck edge setup time t slrs 20 - - ns sdata valid to sclk rising setup time t sdlrs 20 - - ns sclk rising to sdata hold time t sdh 20 - - ns internal sclk mode (note 11) lrck duty cycle (internal sclk only) (note 12) - 50 - % sclk period t sclkw --ns sclk rising to lrck edge t sclkr -- s sdata valid to sclk rising setup time t sdlrs --ns sclk rising to sdata hold time base rate mode t sdh --ns high rate mode t sdh --ns 1 128 () fs --------------------- - 1 64 () fs ------------------ - 1 sclk ---------------- - tsclkw 2 ------------------ 1 512 () fs --------------------- -10 + 1 512 () fs --------------------- -15 + 1 384 () fs --------------------- -15 +
cs43l42 ds481pp2 11 sclkh t slrs t slrd t sdlrs t sdh t sclkl t sdata sclk lrck figure 1. external serial mode input timing figure 2. internal se rial mode input timing *the sclk pulses shown are internal to the cs43l42. sdata *internal sclk lrck sclkw t sdlrs t sdh t sclkr t sdata lrck mclk *internal sclk 1 n 2 n figure 3. internal serial clock generation * the sclk pulses shown are internal to the cs43l42. n equals mclk divided by sclk
cs43l42 12 ds481pp2 switching characteristics - co ntrol port - two-wire mode (t a = 25 c; vl = 1.7 v - 3.6 v; inputs: logic 0 = gnd, logic 1 = vl, c l =30pf) notes: 13. the two-wire mode is compatible with the i 2 c protocol. 14. data must be held for sufficient ti me to bridge the transition time, t fc , of scl. parameter symbol min max unit two-wire mode (note 13) scl clock frequency f scl - 100 khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (p rior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 14) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl t rc -25ns fall time scl t fc -25ns rise time of sda t rd 1s fall time of sda t fd 300 ns setup time for stop condition t susp 4.7 - s t buf t hdst t hdst t lo w t rc t fc t hdd t high t sud t sust t susp stop s tart start stop repeated sda scl t irs rst t rd t fd figure 4. control port timing - two-wire mode
cs43l42 ds481pp2 13 switching characteristics - control port - spi mode (t a = 25 c; vl = 1.7 v - 3.6 v; inputs: logic 0 = gnd, logic 1 = vl, c l =30pf) notes: 15. t spi only needed before first falling edge of cs after rst rising edge. t spi = 0 at all other times. 16. data must be held for sufficient time to bridge the transition time of cclk. 17. for f sck < 1 mhz parameter symbol min max unit spi mode cclk clock frequency f sclk -6mhz rst rising edge to cs falling t srs 500 - ns cclk edge to cs falling (note 15) t spi 500 - ns cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 16) t dh 15 - ns rise time of cclk and cdin (note 17) t r2 -100ns fall time of cclk and cdin (note 17) t f2 -100ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh t spi t srs rst figure 5. control port timing - spi mode
cs43l42 14 ds481pp2 2. typical connec tion diagram mclk lrck sclk/dem1 sdata cp/sa rst sda/cdin/dif0 scl/cclk/dif1 ad0/cs/dem0 c/ digital audio source va va_hp hp_a hp_b aouta aoutb mutec cs43 42 16 ? headphones 1.8to3.3v supply *ferrite bead 1.0 f 0.1 f + + mute circuit va_line 0.9 to 3.3 v supply *ferrite bead 220 220 3.3 f 3.3 f 10 k ? 10 k ? 560 ? 560 ? c c 1.8to3.3v supply 1.0 f 0.1 f + vl *ferrite bead r l r l audio output a audio output b + + + + 18 19 20 6 7 2 5 3 16 21 23 11 1 9 8 22 24 4 17 ? ? 4.7 h 4.7 h mode configuration 1k 1k * * * f f 0.1 f gnd 1.0 f * optional l c= 4 fs(r l + 560 r l 560) vq_hp vq_line filt+ ref_gnd 1.0 f + 12 15 14 13 1.0 f + 1.0 f + figure 6. typical connection diagram
cs43l42 ds481pp2 15 3. register quick reference addrfunction 76543210 0h reserved reserved reserved reserved reserved reserved reserved reserved reserved default 00000000 1h power and muting control amute szc1 szc0 por pdnhp pdnln pdn reserved default 11 0 10010 2h channel a analog headphone attenuation control hvola7 hvola6 hvola5 hvola4 hvola3 hvola2 hvola1 hvola0 default 00000000 3h channel b analog headphone attenuation control hvolb7 hvolb6 hvolb5 hvolb4 hvolb3 hvolb2 hvolb1 hvolb0 default 00000000 4h channel a digital volume control dvola7 dvola6 dvola5 dvola4 dvola3 dvola2 dvola1 dvola0 default 00000000 5h channel b digital volume control dvolb7 dvolb6 dvolb5 dvolb4 dvolb3 dvolb2 dvolb1 dvolb0 default 00000000 6h tone control bb3 bb2 bb1 bb0 tb3 tb2 tb1 tb0 default 00000000 7h mode control bbcf1 bbcf0 tbcf1 tbcf0 a=b dem1 dem0 vcbyp default 00000000 8h limiter attack rate arate7 arate6 arate5 arate4 arate3 arate2 arate1 arate0 default 00010000 9h limiter release rate rrate7 rrate6 rrate5 rrate4 rrate3 rrate2 rrate1 rrate0 default 00100000 ah volume and mixing control tc1 tc0 tc_en lim_en atapi3 atapi2 atapi1 atapi0 default 00001001 bh mode control 2 mclkdiv line1 line0 reserved reserved dif2 dif1 dif0 default 00000000
cs43l42 16 ds481pp2 4. register description note: all registers are read/write in two-wire mode and write only in spi, unless otherwise noted. 4.1 power and muting c ontrol (address 01h) 4.1.1 auto-mute (amute) default = 1 0 - disabled 1 - enabled function: the digital-to-analog converter out put will mute following the reception of 8192 consecutive audio sam- ples of static 0 or -1. a single sample of non- static data will release the mu te. detection and muting is done independently for each channel. the quiescent voltage on the output will be retained and the mute control pin will go active during the mu te period. the muting function is affected, similar to volume control changes, by the soft and zero cross bits in the power and muting control register. 4.1.2 soft ramp and ze ro cross control (szc) default = 10 00 - immediate change 01 - zero cross digital and analog 10 - ramped digital and analog 11 - reserved function: immediate change when immediate change is select ed all level changes will take ef fect immediately in one step. zero cross digital and analog zero cross enable dictates that si gnal level changes, either by atte nuation changes or muting, will occur on a signal zero crossing to minimize audible ar tifacts. the requested level change will occur after a timeout period of 512 sample periods (10.7 ms at 48 kh z sample rate) if the signal does not encounter a zero crossing. the zero cross function is independ ently monitored and implemented for each channel. ramped digital and analog soft ramp allows digital level changes, both muting and attenuation, to be impl emented by incrementally ramping, in 1/8 db steps, from the current level to th e new level at a rate of 1 db per 8 left/right clock pe- riods. analog level changes will occur in 1 db steps on a signal zero crossing. the analog level change will occur after a timeout period of 51 2 sample periods (10.7 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross func tion is independently moni tored and implemented for each channel. note: ramped digital and analog is not available in high-rate mode. 76543210 amute szc1 szc0 por pdnhp pdnln pdn reserved 11010010
cs43l42 ds481pp2 17 4.1.3 popguard? trans ient control (por) default - 1 0 - disabled 1 - enabled function: the popguard ? transient control allows the quiescent voltage to slowly ramp to and from 0 volts to the quiescent voltage during power-on or power-off when this function is enabled. please see section 6.5 for implementation details. 4.1.4 power down headp hone amplifier (pdnhp) default = 0 0 - disabled 1 - enabled function: the headphone amplifier will independently enter a low-power stat e when this func tion is enabled. 4.1.5 power down li ne amplifier (pdnln) default = 0 0 - disabled 1 - enabled function: the line output amplifier will independently enter a low-power st ate when this function is enabled. 4.1.6 power down (pdn) default = 1 0 - disabled 1 - enabled function: the entire device will en ter a low-power state when this function is enabled, and the cont ents of the control registers are retained in this mode. the power-down bi t defaults to ?enabled? on power-up and must be disabled before normal operation will begin.
cs43l42 18 ds481pp2 4.2 channel a analog h eadphone attenuation control (address 02h) (hvola) 4.3 channel b analog h eadphone attenuation control (address 03h) (hvolb) default = 0 db (no attenuation) function: the analog headphone attenuation control operates in dependently from the digital volume control. the analog headphone attenuation control registers allo w attenuation of the head phone output signal for each channel in 1 db increments from 0 to -25 db. attenuation settings are decoded using a 2?s comple- ment code, as shown in table 1. the volume changes are implemented as dictat ed by the soft and zero cross bits in the power and muting control register. all volume settings greater than zero are interpreted as zero. note: the analog headphone attenuatio n only affects the headphone outputs. 4.4 channel a digital volume control (address 04h) (dvola) 4.5 channel b digital volume control (address 05h) (dvolb) default = 0 db (no attenuation) function: the digital volume control register s allow independent control of the signal levels in 1 db increments from +18 to -96 db. volume settings are decoded us ing a 2?s complement code, as shown in table 2. the volume changes are implemented as dictated by the soft and zero cross bits in the power and mut- ing control register. all volume sett ings less than -96 db are equivalent to muting the channel via the atapi bits (see section 4.10.4). note: the digital volume control affects both the line outputs and the headphone outputs. setting this register to values greater than +18 db will cause distortion in the audio outputs. 76543210 hvolx7 hvolx6 hvolx5 hvolx4 hvolx3 hvolx2 hvolx1 hvolx0 00000000 binary code decimal value volume setting 00000000 0 0 db 11110110 -10 -10 db 11110001 -15 -15 db table 1. example analog volume settings 76543210 dvolx7 dvolx6 dvolx5 dvolx4 dvolx3 dvolx2 dvolx1 dvolx0 00000000
cs43l42 ds481pp2 19 4.6 tone control (address 06h) 4.6.1 bass boost level (bb) default = 0 db (no bass boost) function: the level of the shelving bass boost filter is set by bass boost level. the level can be adjusted in 1 db increments from 0 to +12 db of boost. boost levels are decoded as shown in table 3. levels above +12 db are interpreted as +12 db. 4.6.2 treble boost level (tb) default = 0 db (no treble boost) function: the level of the shelving treble boost filter is set by treble boost level. the level can be adjusted in 1 db increments from 0 to +12 db of boost. boost levels are decoded as shown in table 4. levels above +12 db are interpreted as +12 db. note: treble boost is not available in high-rate mode. binary code decimal value volume setting 00001010 12 +12 db 00000111 7 +7 db 00000000 0 0 db 11000100 -60 -60 db 10100110 -90 -90 db table 2. example digital volume settings 76543210 bb3 bb2 bb1 bb0 tb3 tb2 tb1 tb0 00000000 binary code decimal value boost setting 0000 0 0 db 0010 2 +2 db 1010 6 +6 db 1001 9 +9 db 1100 12 +12 db table 3. example bass boost settings binary code decimal value boost setting 0000 0 0 db 0010 2 +2 db 1010 6 +6 db 1001 9 +9 db 1100 12 +12 db table 4. example treble boost settings
cs43l42 20 ds481pp2 4.7 mode control (address 07h) 4.7.1 bass boost co rner frequency (bbcf) default = 00 00 - 50 hz 01 - 100 hz 10 - 200 hz 11 - reserved function: the bass boost corner frequency is user selectable as shown above. 4.7.2 treble boost corner frequency (tbcf) default = 00 00 - 2 khz 01 - 4 khz 10 - 7 khz 11 - reserved function: the treble boost corner frequency is user selectable as shown above. note: treble boost is not available in high-rate mode. 4.7.3 channel a volume = channel b volume (a=b) default = 0 0 - disabled 1 - enabled function: the aouta/hp_a and aoutb/hp_b volume levels are independently controlled by the a and the b channel volume control bytes when this function is disabled. the volume on both aouta/hp_a and aoutb/hp_b are determined by the a channel att enuation and volume control bytes, and the b chan- nel bytes are ignored when this function is enabled. 76543210 bbcf1 bbcf0 tbcf1 tbcf0 a=b dem1 dem0 vcbyp 00000000
cs43l42 ds481pp2 21 4.7.4 de-emphasis control (dem) default = 00 00 - disabled 01 - 44.1 khz 10 - 48 khz 11 - 32 khz function: selects the appropriate digital filter to maintain the standard 15 s/50 s digital de-emphasis filter re- sponse at 32, 44.1 or 48 khz sample rates. (see figure 30) note: de-emphasis is not available in high-rate mode. 4.7.5 digital volume control bypass (vcbyp) default = 0 0 - disabled 1 - enabled function: the digital volume control section is bypassed when this function is enabled. this disables the digital vol- ume control, muting, bass boost, treble boost, limit ing and atapi functions. the analog headphone at- tenuation control will remain functional. 4.8 limiter attack rate (address 08h) (arate) default = 10h - 2 lrck?s per 1/8 db function: the limiter attack rate is user selectable. the rate is a function of sampling frequency, fs, and the value in the limiter attack rate register. rates are calculated using the function rate = 32/{value}, where {value} is the decimal value in the limiter attack rate register and rate is in lrck?s per 1/8 db of change. note: a value of zero in this regist er is not recommended, as it will induce erratic behavior of the limiter. use the lim_en bit to disable the limiter function (see peak signal limiter enable (lim_en) ). 76543210 arate7 arate6 arate5 arate4 arate3 arate2 arate1 arate0 00010000 binary code decimal value lrck?s per 1/8 db 00000001 1 32 00010100 20 1.6 00101000 40 0.8 00111100 60 0.53 01011010 90 0.356 table 5. example limiter attack rate settings
cs43l42 22 ds481pp2 4.9 limiter release rate (address 09h) (rrate) default = 20h - 16 lrck?s per 1/8 db function: the limiter release rate is user sele ctable. the rate is a function of sampling frequency, fs, and the value in the limiter release rate register. rates are calculated using the function rate = 512/{value}, where {value} is the decimal value in the limiter release ra te register and rate is in lrck?s per 1/8 db of change. note: a value of zero in this regist er is not recommended, as it will induce erratic behavior of the limiter. use the lim_en bit to disable the limiter function (see peak signal limiter enable (lim_en) ). 4.10 volume and mixing control (address 0ah) 4.10.1 tone control mode (tc) default = 00 00 - all settings are taken from user registers 01 - 12 db of bass boost at 100 hz and 6 db of treble boost at 7 khz 10 - 8 db of bass boost at 100 hz and 4 db of treble boost at 7 khz 11 - 4 db of bass boost at 100 hz and 2 db of treble boost at 7 khz function: the tone control mode bits determine how the bass boost and treble boost features are configured. the user defined settings from the bass and treble boost level and corner frequency registers are used when these bits are set to ?00?. alternately, one of three pre-defined settings may be used. 4.10.2 tone control enable (tc_en) default = 0 0 - disabled 1 - enabled function: the bass boost and treble boost features ar e active when this function is enabled. 76543210 rrate7 rrate6 rrate5 rrate4 rrate3 rrate2 rrate1 rrate0 00100000 binary code decimal value lrck?s per 1/8 db 00000001 1 512 00010100 20 25 00101000 40 12 00111100 60 8 01011010 90 5 table 6. example limite r release rate settings 76543210 tc1 tc0 tc_en lim_en atapi3 atapi2 atapi1 atapi0 00001001
cs43l42 ds481pp2 23 4.10.3 peak signal limiter enable (lim_en) default = 0 0 - disabled 1 - enabled function: the cs43l42 will limit the maximum signa l amplitude to prevent clipping when this f unction is enabled. peak signal limiting is performed by first decreasing the bass and treb le boost levels. if the signal is still clipping, the digital attenuation is increased. the attack rate is determined by the limiter attack rate register. once the signal has dropped below the clipping level, the attenuation is decreased back to the user se- lected level followed by the bass boost being increased ba ck to the user selected level. the release rate is determined by the limite r release rate register. note: the a=b bit should be set to ?1 ? for optimal limiter performance. 4.10.4 atapi channel mixing and muting (atapi) default = 1001 - aouta/hp_a = l, aoutb/hp_b = r (stereo) function: the cs43l42 implements the channel mixing functions of the atapi cd-rom specif ication. refer to ta- ble 7 and figure 31 for additional information. note: all mixing functions occur prior to the digital volume control. atapi3 atapi2 atapi1 atapi0 aouta/hp_a aoutb/hp_b 0 0 0 0 mute mute 0001 mute r 0010 mute l 0011 mute [(l+r)/2] 0100 r mute 0101 r r 0110 r l 0 1 1 1 r [(l+r)/2] 1000 l mute 1001 l r 1010 l l 1 0 1 1 l [(l+r)/2] 1 1 0 0 [(l+r)/2] mute 1101[(l+r)/2] r 1110[(l+r)/2] l 1 1 1 1 [(l+r)/2] [(l+r)/2] table 7. atapi decode
cs43l42 24 ds481pp2 4.11 mode contro l 2 (address 0bh) 4.11.1 master clock divide enable (mclkdiv) default = 0 0 - disabled 1 - enabled function: the mclkdiv bit enables a circuit which divides the exte rnally applied mclk signal by 2 prior to all other internal circuitry. note: internal sclk is not available when this function is enabled. 4.11.2 line amplifier gain compensation (line) default = 00 00 - 0.785 x va 01 - 0.943 x va 10 - 1.571 x va 11 - line mute function: the line amplifier gain compensation bits allow the user to scale the full-scale li ne output leve l according to the power supply voltag e used. the full-scale line output level will be equal to {gain factor}xva, where {gain factor} is selected from options above. for exam ple, if the user wants t he full-scale line output volt- age to be 1 v rms (2.8 v pp ) with va = 1.8 vdc and va_line = 3.0 vdc, then the gain factor would be 1.571. note: it is possible to exceed the maximum output le vel, limited by va_line, by incorrectly setting the gain compensation factor. the line mute option is available to allow muting of the line output when the hea dphone output is still in use and the line amp is still powered up. to use this f eature, first mute the outputs via the atapi bits. next, set the line gain to line mute. finally, un-m ute the outputs with the atapi bits. following these steps will ensure a click free mute. 4.11.3 digital interface format (dif) default = 000 - format 0 (i 2 s, up to 24-bit data, 64 x fs internal slck) function: the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format and the options are detailed in figures 19-25. note: internal sclk is not available when mclkdiv is enabled. 76543210 mclkdiv line1 line0 reserved reserved dif2 dif1 dif0 00000000
cs43l42 ds481pp2 25 dif2 dif1 dif0 descri ption format figure 000 i 2 s, up to 24-bit data, 64 x fs internal slck 019 001 i 2 s, up to 24-bit data, 32 x fs internal slck 120 010 left justified, up to 24-bit data, 221 011 right justified, 24-bit data 322 100 right justified, 20-bit data 423 101 right justified, 16-bit data 524 110 right justified, 18-bit data 625 111 identical to format 1 120 table 8. digital interface format
cs43l42 26 ds481pp2 5. pin description rst 1 reset ( input ) - the device enters a low power mode and all internal registers are reset to their default settings, including the control port, when low. when high, the control port becomes operational and the pdn bit must be cleared before normal operation will occur. the control port cannot be accessed when reset is low. lrck 2 left/right clock ( input ) - determines which channel is currently being input on the serial audio data input, sdata. the frequency of the left/right clock must be equal to the input sample rate. audio samples in left/right sample pairs will be simultaneously output from the digital-to-analog converter whereas right/left pairs will exhibit a one sample period dif- ference. the required relationship between the left/right clock, serial clock and serial data is defined by the mode control 2 (0bh) register when in control port mode or by the dif1-0 pins when in stand-alone mode. the options are detailed in figures 19-29. sdata 3 serial audio data ( input ) - two's complement msb-first serial data is input on this pin. the data is clocked into sdata via the serial clock and the channel is determined by the left/right clock. the required relationship betwe en the left/right clock, serial clock and serial data is defined by the mode control 2 (0bh ) register when in control port mode or by the dif1-0 pins when in stand-alone mode. the options are detailed in figures 19-29. ad0/cs (control port mode) 4 address bit / chip select ( input ) - in two-wire mode, ad0 is a chip address bit. cs is used to enable the control port interface in spi mode. the device will enter the spi mode anytime a high to low transition is detected on this pin. once the device has entered the spi mode, it will remain in spi mode until ei ther the part is reset or power is removed. sclk 5 serial clock ( input ) - clocks the individual bits of the serial data into the sdata pin. the required relationship between the left/right clo ck, serial clock and serial data is defined by the mode control 2 (0bh) register when in control port mode or by the dif1-0 pins when in stand-alone mode. the options ar e detailed in figures 19-29. the cs43l42 supports both internal and external serial clock generation modes. the inter- nal serial clock mode eliminates possible clock interference from an external sclk. use of the internal serial clock mode is always preferred. internal serial clock mode - in the internal serial clock mode, the serial clock is internally derived and synchronous with the master clo ck and left/right clock. the sclk/lrck fre- quency ratio is either 32, 48, or 64 depending upon the mode control 2 (0bh) register when in control port mode or the dif1-0 pins wh en in stand-alone mode as shown in figures 19-29. operation in this mode is identical to op eration with an external serial clock synchro- nized with lrck. external serial clock mode - the cs43l42 will enter the external serial clock mode when- ever 16 low to high transitions are detected on the sclk pin during any phase of the lrck period. the device will revert to internal serial clock mode if no low to high transitions are detected on the sclk pin for 2 consecutive periods of lrck. reset rst mutec mute control left/right clock lrck aouta analog output a serial data sdata aoutb analog output b ad0/cs /dem0 ad0/cs /dem0 hp_b headphone output b serial clock/dem1 sclk/dem1 va_hp headphone amp power interface power vl va_line line amp power master clock mclk va analog power scl/cclk/dif1 scl/cclk/dif1 gnd ground sda/cdin/dif0 sda/cdin/dif0 hp_a headphone output a no connection n.c. vq_line line out quiescent voltage mode select cp/sa filt+ positive voltage reference hp quiescent voltage vq_hp ref_gnd reference ground 1 2 3 4 5 6 7 8 9 10 11 12 5 1 2 6 24 23 22 21 20 19 18 17 16 15 14 13
cs43l42 ds481pp2 27 dem0 and dem1 (stand-alone mode) 4 and 5 de-emphasis control ( input ) - selects the appropriate digital filter to maintain the standard 15 s/50 s digital de-emphasis filter response at 32, 44.1 or 48 khz sample rates. (see fig- ure 30) when using internal serial clock mode, pin 5 is available for de-emphasis control, dem1, and all de-emphasis filters are available. when using external serial clock mode, pin 5 is not available for de-emphasis use and only the 44.1 khz de-emphasis filter is avail- able. (see table 9) note: de-emphasis is not available in high-rate mode. vl 6 interface power ( input ) - digital interface power supply. typically 1.8 to 3.3 vdc. mclk 7 master clock ( input ) - frequency must be either 256x, 384x, 512x, 768x or 1024x the input sample rate in base rate mode (brm) and 128x, 192x, 256x or 384x the input sample rate in high rate mode (hrm). note that some multiplication factors require setting the mclkdiv bit (see master clock divide enable (mclkdiv) ). tables 10 and 11 illustrate several standard audio sample rates and the required master clock frequencies. scl/cclk (control port mode) 8 serial control interface clock ( input ) - clocks the serial contro l data into or out of sda/cdin. sda/cdin (control port mode) 9 serial control data i/o ( input / output ) - in two-wire mode, sda is a data i/o line. cdin is the input data line for the control port interface in spi mode. internal sclk external sclk dem1 demo description demo description 00 disabled 0 disabled 01 44.1khz 1 44.1 khz 10 48khz 11 32khz table 9. stand alone de-emphasis control sample rate (khz) mclk (mhz) hrm 128x 192x 256x* 384x* 32 4.0960 6.1440 8.1920 12.2880 44.1 5.6448 8.4672 11.2896 16.9344 48 6.1440 9.2160 12.2880 18.4320 64 8.1920 12.2880 16.3840 24.5760 88.2 11.2896 16.9344 22.5792 33.8688 96 12.2880 18.4320 24.5760 36.8640 * requires mclkdiv bit = 1 in mode control 2 register (address 0bh). table 10. hrm common clock frequencies sample rate (khz) mclk (mhz) brm 256x 384x 512x 768x* 1024x* 32 8.1920 12.2880 16.3840 24.5760 32.7680 44.1 11.2896 16.9344 22.5792 32.7680 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520 * requires mclkdiv bit = 1 in mode control 2 register (address 0bh). table 11. brm common clock frequencies
cs43l42 28 ds481pp2 dif1 and dif0 (stand-alone mode) 8 and 9 digital interface format ( input ) - the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format and the options are de- tailed in figures 26-29. n.c. 10 no connection - this pin has no internal connection to the device. cp/sa 11 mode select ( input ) - the mode select pin is used to select control port or stand-alone mode. when high, the cs43l42 will operate in control port mode. when low, the cs43l42 will operate in stand-alone mode. vq_hp 12 headphone quiescent voltage ( output ) - filter connection for internal headphone amp quiescent reference voltage. a capacitor mu st be connected from vq_hp to analog ground, as shown in figure 6. vq_hp is not intend ed to supply external current. vq_hp has a typ- ical source impedance of 250 k ? and any current drawn from this pin will alter device per- formance. ref_gnd 13 reference ground ( input ) - ground reference for the internal sampling circuits. must be connected to analog ground. filt+ 14 positive voltage reference ( output ) - positive reference for internal sampling circuits. an external capacitor is required from filt+ to analog ground, as shown in figure 6. the rec- ommended value will typically provide 60 db of psrr at 1 khz and 40 db of psrr at 60 hz. filt+ is not intended to supply external current. filt+ has a typical source impedance of 250 k ? and any current drawn from this pin will alter device performance. vq_line 15 line out quiescent voltage ( output ) - filter connection for internal line amp quiescent ref- erence voltage. a capacitor mu st be connected from vq_line to analog ground, as shown in figure 6. vq_line is not intended to supply external current. vq_line has a typical source impedance of 250 k ? and any current drawn from this pin will alter device perfor- mance. hp_a and hp_b 16 and 21 headphone outputs ( output ) - the full scale analog headphone output level is specified in the analog characteristics specifications table. gnd 17 ground ( input ) - ground reference. should be connected to analog ground. va 18 analog power ( input ) - analog power supply. typically 1.8 to 3.3 vdc. va_line 19 line amp power ( input ) - line amplifier power supply. typically 1.8 to 3.3 vdc. note: if the line outputs are not used, connect va_line to va. va_hp 20 headphone amp power ( input ) - headphone amplifier power supply. typically 0.9 to 3.3 vdc. aouta and aoutb 22 and 23 analog outputs ( output ) - the full scale analog line output level is specified in the analog characteristics specifications table. mutec 24 mute control ( output ) - the mute control pin goes high during power-up initialization, re- set, muting, power-down or if the master clock to left/right clock frequency ratio is incorrect. this pin is intended to be used as a control for an external mute circuit on the line outputs to prevent the clicks and pops that can occur in any single supply system. use of mute con- trol is not mandatory but recommended for de signs requiring the absolute minimum in ex- traneous clicks and pops. dif1 dif0 description format figure 00 i 2 s, up to 24-bit data 026 01 left justified, up to 24-bit data 127 10 right justified, 24-bit data 228 11 right justified, 16-bit data 329 table 12. digital interface format - dif1 and dif0 (stand-alone mode)
cs43l42 ds481pp2 29 6. applications 6.1 grounding and power supply decoupling as with any high reso lution converter, the cs43l42 requires careful at tention to power sup- ply and grounding arrangements to optimize per- formance. figure 6 shows the recommended power arrangement with va, va_hp, va_line and vl connected to clean supplie s. decoupling capacitors should be located as close to the device package as possible. if desired, al l supply pins may be con- nected to the same suppl y, but a decoupling capac- itor should still be used on each supply pin. 6.2 clock modes the cs43l42 operates in one of two clocking modes. base rate mode supports input sample rates up to 50 khz, and high rate mode supports input sample rates up to 100 khz, see table 10 and 11. all clock modes use 64x oversampling. 6.3 de-emphasis the cs43l42 includes on-ch ip digital de-empha- sis. figure 30 shows the de-emphasis curve for fs equal to 44.1 khz. the fr equency response of the de-emphasis curve will scale proportionally with changes in sample rate, fs. the de-emphasis feature is included to accommo- date older audio recordings that utiliz e pre-empha- sis equalization as a me ans of noise reduction. 6.4 recommended power-up sequence 1) hold rst low until the pow er supply, master clock and left/right clock are stable. in this state, the control port is reset to its default set- tings and vq_hp and vq_line will remain low. set the cp/sa pin at this time. 2) bring rst high. the device will remain in a low power state and latch cp/sa , and vq_hp and vq_line remain low. if cp/sa is high, the control port will be accessible at this time and the desired register settings can be loaded while keeping the pdn bit set to 1. if cp/sa is low, the device will begin the stand-alone pow- er-up sequence 3) (for control port mode ) once the registers are configured as desired, se t the pdn bit to 0, ini- tiating the power-up seque nce. this requires approximately 50 s when the popguard ? transient control (por) bit is set to 0. if the por bit is set to 1, see popguard? transient control for total power-up timing. 6.5 popguard ? transient control the cs43l42 uses popguard ? technology to min- imize the effects of output transi ents during pow- er-up and power-down. this technique minimizes the audio transients commonly produced by sin- gle-ended, single-supply c onverters when it is im- plemented with external dc-blocking capacitors connected in series with the audio outputs. when the device is initially powered-up, the audio outputs, aouta, aoutb, hp_a and hp_b are clamped to gnd. following a delay of approxi- mately 1000 sample periods, each output begins to ramp toward the quiescen t voltage. approximately 10,000 left/right clock cycles later, the outputs reach v q_line and v q_hp respectively, and audio output begins. this gradua l voltage ramping allows time for the external dc-blocking capacitor to charge to the quiescent voltage, minimizing the power-up transient. to prevent transients at power-down, the device must first enter its power- down state. when this oc- curs, audio output ceases and the internal output buffers are disconnected from aouta, aoutb, hp_a and hp_b. in their pl ace, a soft-start current sink is substituted which allows the dc-blocking capacitors to slowly discharge. once this charge is dissipated, the power to th e device may be turned off, and the system is r eady for the next power-on.
cs43l42 30 ds481pp2 to prevent an audio transi ent at the next power-on, the dc-blocking capacitors must fully discharge before turning off the pow er or exiting the pow- er-down state. if full discharge does not occur, a transient will occur when the audio outputs are ini- tially clamped to gnd. th e time that the device must remain in the power -down state is related to the value of the dc-block ing capacitance and the output load. for example, with a 220 f capacitor and a 16 ohm load on the headphone outputs, the minimum power-down time will be approximately 0.4 seconds. use of the mute control function on the line out- puts is recommended for designs requiring the ab- solute minimum in extr aneous clicks and pops. also, use of the mute c ontrol function can enable the system designer to achieve idle channel noise/signal-to-noise rati os only limited by the ex- ternal mute circuit. see the cdb43l42 datasheet for a suggested mute circuit. 7. control port interface the control port is used to load all the internal set- tings. the operation of the control port may be completely asynchronous with the audio sample rate. however, to avoid pot ential interference prob- lems, the control port pins should remain static if no operation is required. the control port has 2 m odes: spi and two-wire, with the cs43l42 operating as a slave device. if two-wire operation is desired, ad0/cs should be tied to vl or gnd. if the cs43l42 ever detects a high to low transition on ad0/cs after power-up, spi mode will be selected. 7.1 spi mode in spi mode, cs is the cs43l42 chip select signal, cclk is the control port bi t clock, cdin is the in- put data line from the microcontroller and the chip address is 0010000. all signals are inputs and data is clocked in on the rising edge of cclk. figure 7 shows the operation of the control port in spi mode. to write to a register, bring cs low. the first 7 bits on cdin form the chip address and must be 0010000. the eighth bit is a read/write indicator (r/w ), which must be low to write. the next 8 bits form the memory address pointer (map), which is set to the address of the re gister that is to be updat- ed. the next 8 bits are the data which will be placed into register desi gnated by the map. the cs43l42 has a map au to increment capabili- ty, enabled by the incr bi t in the map register. if incr is a zero, then the ma p will stay constant for successive writes. if incr is set to a 1, then map will auto increment afte r each byte is written, al- lowing block writes of successive registers. 7.2 two-wire mode in two-wire mode, sda is a bidirectional data line. data is clocked into and out of the part by the clock, scl, with the cloc k to data relationship as shown in figure 8. there is no cs pin. pin ad0 forms the partial chip addr ess and should be tied to vl or gnd as required. th e upper 6 bits of the 7 bit address field must be 001000. to communicate with the cs43l42, the lsb of the chip address field, which is the first byte sent to the cs43l42, should match the setting of the ad0 pin. the eighth bit of the address byte is the r/w bit (high for a read, low for a write). if the operation is a write, the next byte is the memory address pointer, map, which selects the register to be read or written. the map is then followed by the data to be written. if the operation is a read, the contents of the register pointed to by the map will be output after the chip address. the cs43l42 has map auto increment capability, enabled by the incr bit in the map register. if incr is 0, then the map wi ll stay constant for suc- cessive writes. if incr is set to 1, then map will auto increment after each byte is written, allowing block reads or writes of successive registers. the two-wire mode is compatible with the i 2 c protocol.
cs43l42 ds481pp2 31 7.3 memory address pointer (map) 7.3.1 incr (auto map increment enable) default = ?0? 0 - disabled 1 - enabled 7.3.2 map0-3 (mem ory address pointer) default = ?0000? 76543210 incr reserved reserved reserved map3 map2 map1 map0 00000000 map msb lsb data byte 1 byte n r/w map = memory address pointer address chip cdin cclk cs 0010000 figure 7. control port timing, spi mode sda scl 001000 addr ad0 r/w start ack data 1-8 ack data 1-8 ack stop note: if operation is a write, this byte contains the memory address pointer, map. note 1 figure 8. control port timing, two-wire mode
cs43l42 32 ds481pp2 figure 9. base-rate stopband reject ion figure 10. base-rate transition band figure 11. base-rate transi tion band (detail) figure 12. base-rate passband ripple -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequency (normalized to fs) amplitude db -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.6 0 frequency (normalized to fs) amplitude db figure 13. high-rate stopband rejectio n figure 14. high-rate transition band
cs43l42 ds481pp2 33 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.5 5 frequency (normalized to fs) amplitude db -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.5 0 frequency (normalized to fs) amplitude db figure 15. high-rate transition band (d etail) figure 16. high-rate passband ripple aoutx agnd 3.3 f v out r l c l + figure 17. line output test load hp_x agnd 220 f v out r l c l + figure 18. headphone output test load
cs43l42 34 ds481pp2 lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 internal sclk mode external sclk mode i 2 s, up to 24-bit data and int sclk = 64 fs if mclk/lrck = 512, 256 or 128 i 2 s, up to 24-bit data and int sclk = 48 fs if mclk/lrck = 384 or 192 i 2 s, up to 24-bit data data valid on rising edge of sclk figure 19. cs43l42 control port mode - serial audio format 0 figure 20. cs43l42 control port mode - serial audio format 1 lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 internal sclk mode external sclk mode i 2 s, 16-bit data and int sclk = 32 fs if mclk/lrck = 512, 256 or 128 i 2 s, up to 24-bit data and int sclk = 48 fs if mclk/lrck = 384 or 192 i 2 s, up to 24-bit data data valid on rising edge of sclk figure 21. cs43l42 control port mode - serial audio format 2 lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 internal sclk mode external sclk mode left justified, up to 24-bit data int sclk = 64 fs if mclk/lrck = 512, 256 or 128 int sclk = 48 fs if mclk/lrck = 384 or 192 left justified, up to 24-bit data data valid on rising edge of sclk
cs43l42 ds481pp2 35 figure 22. cs43l42 control port mode - serial audio format 3 lrck sclk left channel sdata 6543210 7 23 22 21 20 19 18 6543210 7 23 22 21 20 19 18 32 clocks 0 right channel internal sclk mode external sclk mode right justified, 24-bit data int sclk = 64 fs if mclk/lrck = 512, 256 or 128 int sclk = 48 fs if mclk/lrck = 384 or 192 right justified, 24-bit data data valid on rising edge of sclk sclk must have at least 48 cycles per lrck period figure 23. cs43l42 control port mode - serial audio format 4 lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 32 clocks 19 18 19 18 internal sclk mode external sclk mode right justified, 20-bit data int sclk = 64 fs if mclk/lrck = 512, 256 or 128 int sclk = 48 fs if mclk/lrck = 384 or 192 right justified, 20-bit data data valid on rising edge of sclk sclk must have at least 40 cycles per lrck period figure 24. cs43l42 control port mode - serial audio format 5 lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 32 clocks internal sclk mode external sclk mode right justified, 16-bit data int sclk = 32 fs if mclk/lrck = 512, 256 or 128 int sclk = 48 fs if mclk/lrck = 384 or 192 right justified, 16-bit data data valid on rising edge of sclk sclk must have at least 32 cycles per lrck period
cs43l42 36 ds481pp2 figure 25. cs43l42 control port mode - serial audio format 6 lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 32 clocks internal sclk mode external sclk mode right justified, 18-bit data int sclk = 64 fs if mclk/lrck = 512, 256 or 128 int sclk = 48 fs if mclk/lrck = 384 or 192 right justified, 18-bit data data valid on rising edge of sclk sclk must have at least 36 cycles per lrck period lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 internal sclk mode external sclk mode i 2 s, up to 24-bit data and int sclk = 64 fs if mclk/lrck = 512, 256 or 128 i 2 s, up to 24-bit data and int sclk = 48 fs if mclk/lrck = 384 or 192 i 2 s, up to 24-bit data data valid on rising edge of sclk figure 26. cs43l42 stand alone mode - serial audio format 0 figure 27. cs43l42 stand alone mode - serial audio format 1 lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 internal sclk mode external sclk mode left justified, up to 24-bit data int sclk = 64 fs if mclk/lrck = 512, 256 or 128 int sclk = 48 fs if mclk/lrck = 384 or 192 left justified, up to 24-bit data data valid on rising edge of sclk
cs43l42 ds481pp2 37 figure 28. cs43l42 stand alone mode - serial audio format 2 lrck sclk left channel sdata 6543210 7 23 22 21 20 19 18 6543210 7 23 22 21 20 19 18 32 clocks 0 right channel internal sclk mode external sclk mode right justified, 24-bit data int sclk = 64 fs if mclk/lrck = 512, 256 or 128 int sclk = 48 fs if mclk/lrck = 384 or 192 right justified, 24-bit data data valid on rising edge of sclk sclk must have at least 48 cycles per lrck period figure 29. cs43l42 stand alone mode - serial audio format 3 lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 32 clocks internal sclk mode external sclk mode right justified, 16-bit data int sclk = 32 fs if mclk/lrck = 512, 256 or 128 int sclk = 48 fs if mclk/lrck = 384 or 192 right justified, 16-bit data data valid on rising edge of sclk sclk must have at least 32 cycles per lrck period
cs43l42 38 ds481pp2 gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 30. de-emphasis curve volume control aouta/hp_a aoutb/hp_b left channel audio data right channel audio data volume control mute mute eq eq digital a channel digital b channel figure 31. atapi block diagram
cs43l42 ds481pp2 39 8. parameter definitions total harmonic distorti on + noise (thd+n) the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 hz to 20 khz), including distortion components. expressed in decibels. dynamic range the ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to- noise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distor tion components are below the noise level and do not effect the measurement. this measurement technique has been accepted by the audio engineering so- ciety, aes17-1991, and the electronic industries asso ciation of japan , eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right cha nnels. measured for each channel at the converter's output with all zeros to the input under test and a fu ll-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full scale analog output for a full scale digital input. gain drift the change in gain value with temperature. units in ppm/c. 9. references 1) "how to achieve optimu m performance from delt a-sigma a/d & d/a convert ers" by steven harris. paper presented at the 93rd convention of the audio engineering society, october 1992. 2) cdb43l42 evaluation board datasheet 3) ?the i 2 c-bus specification: version 2.0? philips semiconducto rs, december 1998. http://www.semic onductors.philips.com
cs43l42 40 ds481pp2 10. package dimensions notes: 1. ?d? and ?e1? are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension ?b? does not include dambar protrusion /intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximu m material condition. dambar intrusion shall not reduce dimension ?b? by more than 0.07 mm at least material condition. 3. these dimensions apply to the fl at section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a -- -- 0.043 -- -- 1.10 a1 0.002 0.004 0.006 0.05 -- 0.15 a2 0.03346 0.0354 0.037 0.85 0.90 0.95 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 d 0.303 0.307 0.311 7.70 7.80 7.90 1 e 0.248 0.2519 0.256 6.30 6.40 6.50 e1 0.169 0.1732 0.177 4.30 4.40 4.50 1 e -- 0.026 bsc -- -- 0.65 bsc -- l 0.020 0.024 0.028 0.50 0.60 0.70 0 4 8 0 4 8 jedec #: mo-153 controlling dimensi on is millimeters. 24l tssop (4.4 mm body) package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view

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